A major milestone along the way is the demonstration of quantum computational advantage, which is known as quantum supremacy. It is defined by a quantum device that can implement a well-defined task overwhelmingly faster than any classic computer to an extent that no classical computer can complete the task within a reasonable amount of time.
Increasing the number of qubits and high-fidelity quantum logic gates are also crucial for the rapid development of noisy intermediate scale quantum (NISQ) [1] and demonstration of logic qubit through surface code error correction.
Scaling up high-fidelity superconducting quantum processors faces major challenges in the chip fabrication and qubit control.
The Zuchongzhi quantum processor consists of 66 qubits, arrayed in 11 rows and 6 columns forming a two dimensional rectangular lattice pattern as depicted in the device schematic in Fig. (a)
The quantum processor uses Transmon qubits , which are essentially non-linear oscillators with their non-linearity originating from superconducting Josephson effect.
The lowest two energy levels of the non-linear oscillator are singled out to form the computational space of a qubit, encoded as |0> and |1>. Each qubit has two control lines to provide full control of the qubit: a microwave drive line to drive excitations between |0> and |1>, and a magnetic flux bias line to tune the qubit resonance frequency. Each qubit, except those at the boundaries, has four tunable couplers to couple to its nearest neighbors, has four tunable couplers to couple to its nearest neighbors, with tunable coupling that can be turned on nd off with fast control. The tunable couplers are also Transmon qubits, which frequencies several GHz higher than that of the data qubits and always stays at ground states. A magnetic flux bias line is provided for each coupler to fast tune the coupling strength g between neighboring qubit continually from ~ +5MHz to ~-50MHz. Each qubit dispersively couples to a readout resonator which couples to a Purcell filter shared between six qubits, frequency multiplexing is used to readout the qubit states simultaneously.
[1] https://quantumcomputing.stackexchange.com/questions/1885/what-is-meant-by-noisy-intermediate-scale-quantum-nisq-technology
When we talk about quantum computers, we usually mean fault-tolerant devices. These will be able to run Shor's algorithm for factoring, as well as all the other algorithms that have been developed over the years. But the power comes at a cost: to solve a factoring problem that is not feasible for a classical computer, we will require millions of qubits. This overhead is required for error correction, since most algorithms we know are extremely sensitive to noise.
Even so, programs run on devices beyond 50 qubits in size quickly become extremely difficult to simulate on classical computers. This opens the possibility that devices of this sort of size might be used to perform the first demonstration of a quantum computer doing something that is infeasible for a classical one. It will likely be a highly abstract task, and not useful for any practical purpose, but it will nevertheless be a proof-of-principle.
Once this is done, we'll be in a strange era. We'll know that devices can do things that classical computers can't, but they won't be big enough to provide fault-tolerant implementations of the algorithms we know about. Preskill coined the term 'Noisy Intermediate-Scale Quantum' to describe this era. Noisy because we don't have enough qubits to spare for error correction, and so we'll need to directly use the imperfect qubits at the physical layer. And 'Intermediate-Scale' because of their small (but not too small) qubit number.
So what applications might devices in NISQ era have? And how will we design the quantum software to implement them? These are questions that are far from being fully answered, and will likely require quite different techniques than those for fault-tolerant quantum computing.
